from machine import FPIOA
from machine import Pin
from machine import SPI
from machine import UART
import time



spi = FPIOA()
pin = FPIOA()
uart = FPIOA()


############################# SPI0 moudle1 Configure start ####################
pin.help(48)
pin.set_function(48, pin.GPIO48)
pin.help(48)
pin.help(49)
pin.set_function(49, pin.GPIO49)
pin.help(49)

spi.help(14)
#spi.set_function(14,spi.QSPI0_CS0)          #SPI1 CS
pin.set_function(14, pin.GPIO14)
spi.help(14)

spi.help(15)
spi.set_function(15,spi.QSPI0_CLK)          #SPI1 CLK
spi.help(15)

spi.help(16)
spi.set_function(16,spi.QSPI0_D0)           #SPI1 D0
spi.help(16)

spi.help(17)
spi.set_function(17,spi.QSPI0_D1)           #SPI1 D1
spi.help(17)

uart.set_function(11, uart.UART2_TXD)
uart.set_function(12, uart.UART2_RXD)

IRQ = Pin(48, Pin.IN, pull = Pin.PULL_NONE)                    #moudle1 irq
CE  = Pin(49, Pin.OUT, pull = Pin.PULL_NONE, drive = 7)        #moudle1 CE
CS  = Pin(14, Pin.OUT, pull = Pin.PULL_NONE, drive = 7)        #moudle1 CS
CS.high()

############################# SPI0 moudle1 Configure end ####################



module0 = SPI(1, baudrate = 10000000, polarity = 0, phase = 0, bits = 8)

uart2 = UART(UART.UART2, baudrate = 115200, bits=UART.EIGHTBITS, parity=UART.PARITY_NONE, stop=UART.STOPBITS_ONE)


def moduleWriteReg(dev, reg, val):
    data = bytearray(2)
    data[0] = 0x20 | reg
    data[1] = val

    CS.low()
    dev.write(data)
    CS.high()
    print("write reg:{0},value:{1}".format(hex(data[0]), hex(data[1])))

def moduleReadReg(dev, reg, buf):
    data = bytearray(2)
    data[0] = reg
    data[1] = 0xFF

    CS.low()
    dev.write_readinto(data, buf)
    CS.high()
    print("read reg:{0}, ststus:{1}, value:{2}".format(hex(data[0]), hex(buf[0]), hex(buf[1])))

def moduleWriteCmd(dev, opt, buf, len):
    data = bytearray(len + 1)
    i = 0
    while i < len + 1:
        if i == 0:
            data[i] = opt
        else:
            data[i] = buf[i - 1]
        i = i + 1
    CS.low()
    dev.write(data)
    CS.high()
    print("write opt:", hex(data[0]))
    print("data: ", data[1:len+1])


def moduleReadCmd(dev, opt, buf, len):
    data = bytearray(len + 1)
    i = 0
    while i < len:
        if i == 0:
            data[i] = 0x00 | opt
        else:
            data[i] = 0xff
        i = i + 1
    CS.low()
    dev.write_readinto(data, buf)
    CS.high()
    print("read opt:", hex(buf[0]))
    print("data: ", buf[1:len+1])

readReg = bytearray(2)
addr1 = bytearray(6)
addr2 = bytearray(6)
sendaddr = bytes([0xe5, 0xe5, 0xe5, 0xe5, 0xe5])
recvaddr = bytes([0xe7, 0xe7, 0xe7, 0xe7, 0xe7])
sendBuf = bytes([0x01, 0x02, 0x03, 0x04, 0x05, 0x06])

print("start")
time.sleep_ms(100)
moduleReadCmd(module0, 0x10, addr1, 5)
moduleWriteReg(module0, 0x03, 0x03)
moduleReadReg(module0, 0x03, readReg)

#moduleReadCmd(module0, 0x10, addr1, 5)
moduleWriteCmd(module0, 0x10 | 0x20, sendaddr, 5)
moduleReadCmd(module0, 0x10, addr1, 5)

moduleWriteCmd(module0, 0x0A | 0x20, recvaddr, 5)
moduleReadCmd(module0, 0x0A, addr2, 5)


#moduleReadReg(module0, 0x02, readReg)
#moduleReadCmd(module0, 0x0A, addr1, 5)
moduleWriteReg(module0, 0x02, 0x01)
moduleWriteReg(module0, 0x1D, 0x05)

moduleWriteReg(module0, 0x00, 0x0A)
#moduleReadReg(module0, 0x00, readReg)
time.sleep_ms(5)
CE.value(1)                             #进入发送模式
time.sleep_ms(5)
while True:
    moduleWriteCmd(module0, 0xB0, sendBuf, 6)
    print("send:",sendBuf)
    if 0 == IRQ.value():
        moduleReadReg(module0, 0x07, status)
        print("status: ", hex(status))
    time.sleep_ms(500)

'''
    status = bytearray(2)
    recvLen = bytearray(2)
    recvBuf = bytearray(32)
    if 0 == IRQ.value():
        moduleReadReg(module0, 0x07, status)
        if (status[0] & 0x40) == 0x40:
            moduleReadReg(module0, 0x11, recvLen)
            moduleReadCmd(module0, 0x61, recvBuf)
            print("recv: ", recvBuf)
            moduleWriteReg(module0, 0x07, 0x40)

    print("irq state:", IRQ.value())
    time.sleep_ms(500)
'''
